NP-1 “Apex” is a 4 nm neural-processor for sustained on-device inference. It runs transformer and convolutional workloads at the edge — no host offload, no network round-trip. Specifications below are engineering-silicon figures.
PeakStack 3.2 · batch 64 · median of 1,000 runs · 25 °C ambient.
Weight-only INT4 · FP16 KV cache · batch 1 · single decode token.
The memory wall, not compute, bounds most edge-inference latency. NP-1 keeps weights resident in on-chip SRAM so the MAC array is never idle waiting on an external bus. LPDDR5X handles the long tail: activations, KV cache, and multi-tenant context.
On-chip aggregate ~2 TB/s vs 256 GB/s off-chip. Full subsystem in the architecture document.
Toolchain release adds 2:4 structured-sparsity kernels for FP4, a scheduler pass for the 2-D mesh, and a drop-in ONNX Runtime execution provider.
Mid-range part moves from sampling to GA across commercial and industrial temperature grades.
Engineering samples pass functional bring-up across the full die: PCIe, memory PHY, and all 16 processing elements.
The SRAM-first architecture is what closed the deal for us. Our latency budget stopped being a negotiation with the memory controller.
We moved from host offload to fully on-device and the power envelope barely moved. That is the number our customers actually care about.