Announcements from the lab and a versioned changelog. We publish numbers only once they're measured on production silicon — if a post says "up to," that's a ceiling, not a promise.
Our next-generation die is powered up and passing the first functional vectors. Bring-up is early, but the tiled compute array is already running transformer workloads at a rate that changes what we can promise at the same power envelope. We'll publish measured numbers once they're on production silicon — not from simulation, and not before.
On-device LLM inference joins the toolchain. INT4 weight quantization, activation sparsity, and a KV-cache path tuned for the on-die SRAM. A 1.5B-parameter model now decodes at 40 tokens/s on a single NP-1 inside a single-digit watt envelope.
We rebuilt the reference design around thermal headroom. The new board fits a sealed industrial housing with no fan and no vent, holding the full NP-1 performance envelope across -40 °C to 105 °C junction. What that unlocks for field-hardened equipment is the point of the post.
Expanded thermal characterization, BF16 support documented, and a full electrical spec for the LPDDR5 PHY. Nothing changed on the die — this is documentation catching up with what the silicon already does.
The compact vision processor moves from engineering samples to first design-ins with camera and sensor partners. Sub-4 mm package, 1.5 W typical, and the same toolchain as NP-1 — a model compiled for one runs on the other.
Automatic weight and activation sparsity, and a mixed-precision policy engine, ship to all partners. One calibration pass, a per-layer precision policy, flash — no hand-written kernels.
Software and silicon, in the order they shipped. Datasheet revisions are tracked separately from silicon revisions — a datasheet change doesn't always mean a new die.
INT4 weight quantization, activation sparsity, and a KV-cache scheduler tuned for on-die SRAM. Adds a decode path for on-device language models.
A sparsity pass applied without touching model code, and a per-layer precision policy engine. The first release with hardware-in-the-loop profiling as default.
PyTorch and ONNX import, INT8 and FP16, calibration-aware quantization, and the one-pass-to-flash flow that's still the backbone of the toolchain.
First silicon returned from the fab and passing initial functional vectors. Numbers to follow on production silicon.
Documentation release. BF16 support, LPDDR5 electrical specification, and expanded junction-temperature characterization. No die change.
Engineering samples to first design-ins. Shares NP-ISA v2 and the PeakStack toolchain with NP-1.
First design wins ship in robotics and smart-camera systems. PeakStack reaches a stable 1.0 alongside it.