Whitepapers carry the doc number and revision, because that is how a datasheet ages. Documentation is gated to design partners; the abstracts below are public.
The die floorplan, the processing-element microarchitecture, the three-tier memory hierarchy, and the 2-D mesh NoC. The document the datasheet points to.
Request access →How 2:4 structured sparsity is represented, pruned, and decoded on-chip — and why it is deterministic rather than data-dependent.
Request access →Weight-only and activation quantization for the five on-array precisions, with the accuracy budget and the failure cases, stated plainly.
Request access →The lowering pipeline — graph partitioning, operator fusion, mesh placement, and memory liveness — that turns a model export into a resident graph.
Request access →The bandwidth and latency tiers in detail, and the weight-stationary versus activation-stationary dataflow choices per workload class.
Request access →Whitepapers are distributed under NDA to registered design partners. Apply for access.
One toolchain across NP-1, NP-2, and NP-4. A model compiled for one runs on all three.
Lowers ONNX / PyTorch / TensorFlow Lite into a resident graph. Operator fusion, sparsity planning, mesh placement.
x86_64 · LinuxWeight-only and activation quantization to INT8 / INT4 / FP8 / FP4, with per-layer calibration and an accuracy report.
CLI · PythonCycle-accurate model of the die for pre-silicon development and NP-4 bring-up.
RTL-accurateHost runtime and kernel driver. Loads a compiled graph, manages memory, and drives the PCIe interface.
Linux · RTOSA drop-in ONNX Runtime execution provider so existing pipelines can target NP silicon without a rewrite.
interopBoot image, kernel, and example graphs for the evaluation kit.
board supportSDK access is free for design partners and issued with the evaluation kit. We do not gate it behind a marketing funnel — but we do ask who is building with it.
| Document | Code | Rev | Status |
|---|---|---|---|
| NP-1 Apex datasheet | NP1-DS-001 | 1.2 | Engineering silicon |
| NP-2 Crest datasheet | NP2-DS-002 | 1.0 | GA |
| NP-4 Ridge datasheet (target) | NP4-DS-004 | 0.9 | Pre-silicon |
| EVK-1 evaluation kit guide | EVK-1-UG | 1.1 | Available |
| NP-1 reference design (schematics + layout) | NP1-RD-001 | 1.0 | Design partners |
| PeakStack compiler reference | PS-REF-003 | 3.2 | Available |