Hardware — NeuralPeak

NP-1 — flagship edge inference processor

Transformer-class compute in a single-digit watt envelope.

The full-size part, built for robotics, multi-camera systems, and any platform that needs headroom for modern models.

NP-1 · datasheet summaryrev 2.4

Process node	6 nm-class
Peak compute	Up to 40 TOPS INT8 · 20 TOPS FP16 (sparse-aware)
On-chip memory	18 MB SRAM (L2)
External memory	LPDDR4X / LPDDR5 · up to 68 GB/s
Typical power	8 W (sustained inference) · 12 W peak
Idle power	< 0.8 W
Package	14 × 14 mm BGA, 0.5 mm pitch
Operating temp	-40 °C to 105 °C junction
Host interfaces	PCIe Gen3 ×4 · 2× 10G Ethernet · 4× MIPI CSI-2 (4-lane)
Memory subsystem	18 MB L2 SRAM (banked, dual-port) · per-tile scratchpad · LPDDR4X / LPDDR5
Memory protection	Inline ECC on SRAM and LPDDR data paths
Instruction set	NP-ISA v2 — tensor, vector, and DMA instructions
Security	Secure boot · inline memory-encryption engine · hardware key store
Formats	INT8, INT4, FP16, BF16

Specifications are typical values at nominal voltage and 25 °C ambient, unless otherwise noted. Peak figures are theoretical ceilings; sustained figures are reported on the performance page.

Tiled compute array — 64 systolic tiles with on-die SRAM
Dedicated vector engine for non-tensor ops (activation, normalization)
Lightweight control plane that doesn't touch the data path
Deterministic NoC — bounded, predictable routing latency
Hardware zero-skipping scheduler for sparse activations

NP-C1 — compact vision processor

The same engine, scaled for a lens housing.

For smart cameras, doorbells, and sensor nodes where the whole compute budget has to fit inside a few square centimeters.

NP-C1 · datasheet summaryrev 1.8

Process node	6 nm-class
Peak compute	Up to 8 TOPS INT8 · 4 TOPS FP16
On-chip memory	4 MB SRAM
External memory	LPDDR4X · up to 12 GB/s
Typical power	1.5 W (sustained) · 2.5 W peak
Idle power	< 0.15 W
Package	4 × 4 mm wafer-level, 0.4 mm pitch
Operating temp	-20 °C to 85 °C ambient
Host interfaces	1× MIPI CSI-2 (4-lane) · USB 2.0 · SPI
Memory subsystem	4 MB SRAM (banked) · LPDDR4X
Memory protection	Inline ECC on SRAM
Instruction set	NP-ISA v2 — same toolchain as NP-1
Security	Secure boot · hardware key store
Formats	INT8, INT4, FP16

Typical values at nominal voltage and 25 °C ambient. NP-C1 shares the NP-1 instruction set and toolchain — a model compiled for one runs on the other.

Memory subsystem

Weights stay on the die; the bus stays quiet.

The memory hierarchy is sized so a model's hot weights live in SRAM, not in DRAM. That's the difference between deterministic latency and "usually fast."

Per-tile scratchpad: a small local SRAM at each of the 64 systolic tiles, wide enough to feed the array without stalling.
L2 SRAM (18 MB on NP-1): banked and dual-port, holding resident weights so a steady-state inference never refetches from DRAM.
LPDDR4X / LPDDR5 (NP-1): up to 68 GB/s for weight streaming, activation spill, and multi-model residency.
Deterministic arbitration on the NoC — the scheduler guarantees a bound on worst-case memory latency, which is what a control loop needs.
Inline ECC on every SRAM and DRAM path: silent data corruption is a functional failure, not an acceptable error rate.

Instruction set

NP-ISA: small enough to reason about, complete enough to compile to.

The instruction set is fixed-width and deliberately compact. It has just the operations a neural engine needs — nothing general-purpose — which is how the control plane stays out of the data path. You won't hand-write it; the compiler will.

NP-ISA v2 · instruction groupstargeted by PeakStack

Tensor	Tiled GEMM, convolution, and attention primitives over the systolic array
Vector	Elementwise activation, normalization, and reduction on the vector engine
Memory	DMA and descriptor-based movement between scratchpad, L2, and DRAM
Control	Synchronization barriers, zero-skip predicates, and precision-cast hints
Sparse	Compressed-weight and sparse-activation dispatch, decoded in hardware

NP-C1 executes a subset of NP-ISA v2 — anything PeakStack compiles for it runs unchanged on NP-1.

Precision & formats

Choose precision per layer, not per model.

Mixed-precision inference lets a single model keep its sensitive layers in FP16 while running the bulk in INT8 — accuracy and throughput at once.

INT8

Peak throughput. The workhorse for CNNs and vision transformers.

INT4

Half the bandwidth for weight-bound layers and on-device LLMs.

FP16

Full precision for accuracy-critical heads and detection.

BF16

Training-free fine-tuning and calibration workloads (NP-1).

PeakStack

From PyTorch to flash in one pass.

The toolchain is a compiler, not a runtime puzzle. Export from PyTorch or ONNX, run one calibration pass, and flash. No hand-writing kernels, no per-platform rewrites.

Import: PyTorch (TorchScript / torch.export) and ONNX — one graph, no per-framework glue
Calibration-aware quantization with a per-layer precision policy: INT8 for the bulk, FP16 for accuracy-critical heads
Automatic weight and activation sparsity, applied without touching your model code
Static scheduling: the compiler lays out every operator against the memory hierarchy before the chip runs
Hardware-in-the-loop profiling on the evaluation board — numbers come from the die, not a cycle model
Same binary runs on NP-1 and NP-C1 — scale without recompiling